The present invention relates generally to semiconductor devices, and more particularly, to a digital phase interpolator and a semi-digital delay locked loop (DLL) incorporating same.
Numerous semiconductor devices use specialized circuits to adjust timing delays for input/output (I/O) signals, clock signals, etc. The digital phase interpolator is one such circuit and is commonly used to adjust the timing of internal clock signal(s) within semiconductor devices.
The digital phase interpolator receives two input signals having different phases and generates an output signal having a defined phase between the two received input signals. The digital phase interpolator may be implemented in a simple circuit, and can precisely output a defined phase. As a result, the digital phase interpolator is used in various semiconductor devices applications and circuits, such as a semi-digital DLL. One conventional example of a digital phase interpolator is disclosed in U.S. Pat. No. 6,727,741.
However, conventional digital phase interpolators always receive one input signal before the other. Thus, one input signal has a leading phase relative to the other input signal phase. This operational result is fine for some applications, but presents a problem for other applications and circuit. For example, when the relative (lead/lag) phases for two input signals received by a digital phase interpolator, such as one incorporated within a semi-digital DLL, continuously change, it is difficult to track which one of the two input signals is first received, and the conventional digital phase interpolator becomes difficult to use.